This invention relates to methods for processing semiconductor materials, and in particular to methods for measuring the amount of alignment offset problems in the fabrication of a semiconductor which exist between an interconnect layer and a layer having opening therein such as vias or the like, and provides for effective and efficient electrical and visual alignment confirmation of the location of the openings.
Today's semiconductor technology has been advancing in a direction that requires ever increasing numbers of interconnections with integrated circuits. Typically a large number of integrated circuits are formed on a silicon wafer. Then, they are sliced into individual integrated circuit dies (or chips). Each die is then packaged and used. Electrical connections to the dies are made in one of a few ways. In one type of package, a die receiving area (or die receiving cavity) is provided in the package to receive an integrated circuit die. A number of conductive lines (traces or leads) whose outer ends are electrically connected to pins or leads on the package extend inward towards the die receiving area, usually in a radial pattern, stopping just short of the periphery of the die. The die has a number of "bond pads" for the purpose of making electrical connections with the inner ends of the conductive lines, and is mounted such that the bond pads are exposed. The inner ends of these conductive traces or leads are positioned such that they form an array of connection points surrounding the die. Very thin "bond wires", usually formed of a metal such as aluminum or gold, are then used to connect the connections points on a one for one basis with the bond pads on the integrated circuit die. After mounting, the area or cavity containing the die and the bond wires is usually sealed with a cover or an encapsulant to protect the die and the bond wires from ambient moisture or physical damage.
Semiconductor integrated circuits undergo a variety of processing steps during manufacture, such as masking, resist coat, etching, and deposition. In many of these steps, material is overlayed or removed from the existing layer at specific locations in order to form the desired elements of the integrated circuit. Proper alignment of the various process layers is therefore critical. The shrinking dimensions of modern integrated circuits require increasingly stringent overlay alignment accuracy. If the proper alignment tolerance is not achieved, a device can result which is defective or has reliability problems. More specifically, semiconductor processes such as described above employ fabrication steps in which aligned openings are formed in contact layers and multiple interconnect layers to complete an electrical connection. The interconnect layer is typically a metal layer and the contact layer or via layer is typically an insulating/dielectric layer Registration is typically used to measure the accuracy of a process layer alignment performed using an alignment mark. Registration involves comparing the position of a subsequent layer to that of an existing layer by overlaying a distinct pattern on a matching pattern previously formed on the existing layer. The deviation in position of the overlay from the original provides a measure of accuracy of the alignment. Currently available registration structures include box-in-box visual verniers to determine the extent of registration, i.e., the amount of alignment offset. Automatic Measurement Systems ("AMS") and Canomap, each of which uses a different type of structure or pattern for comparison.
Under current practice using alignment marks, optimization of alignment of respective openings involves testing mark sizes and shapes. Subsequent registration of respective test wafers are used to verify the alignment using the alignment mark. One existing method to optimize an alignment mark uses a waferstepper test reticle with a single type of alignment mark to generate a first process layer, followed by printing the second layer resist pattern, and then performing registration on an overlay in both X and Y directions. The mark which results in the "best registration" reading is chosen as the optimal mark.
However, this and other similar techniques have a number of disadvantages. For example, the measurement results do not provide information regarding the position of the alignment marks within acceptable process performance specifications. Another problem is that a full array of alignment marks and registration overlays are not available to test. Furthermore, layer process variations which may effect the overlay are not taken into account in the measurements. Thus, none of the currently available registrability measurement techniques determine whether a particular alignment mark is indeed optimal. In order to get overlay registration measurements from different alignment mark sizes, the test wafers must be stripped, re-spun and re-exposed several times. This could potentially alter the film surface and thereby affect alignment measurement results. In order to optimize other types of alignment marks, a different set of test wafers would have to be generated using a different test reticle. Furthermore, the test reticles do not include the capability for orthogonal measurements, which means that measurement results are considerably more difficult to model mathematically. These drawbacks limit the achievable alignment accuracy, and result in significantly increased manufacturing costs and greater likelihood of device defects.
As previously described above, visual alignment targets with box in box method are generally used to visually determine the alignment accuracy of contact layer openings to the underlying layers (See FIG. 1A).
A separate electrical structure with contact chains layout in both X and Y direction to detect the alignment accuracy (see FIGS. 1B & 1C).
Thus, the discontinuous structural patterns, such as the box in box design described above, are used for separately performing the functions of (a) visual inline alignment confirmation and (b) electrical measurement with scribeline structure at end of line to determine the accuracy of the alignment during manufacturing. This has made it very difficult to correlate the alignment accuracy of the openings to the underlining layer due to the sensitivity and difference in the structures.
There is thus a need that exists for a system and method for reducing alignment offset problems between an interconnect layer and/or contact layer and the layer containing the openings.